1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a ferroelectric memory device having a plurality of sets of bit lines, to which are connected a plurality of memory cells made up of one capacitor using a ferroelectric film and one MOS transistor, and differential sense amplifiers that can be connected to said bit lines. The ferroelectric memory device stores information by making the direction of polarization of the ferroelectric film correspond to binary information.
2. Description of the Related Art
In a ferroelectric memory device using a one-transistor one-capacitor type (lTlC type) memory cell, a reference voltage must be generated to determine whether data read from the memory cell is logic "0" or logic "1". One type of device employs a dummy cell. One example of such a dummy cell construction is disclosed in Japanese Patent Laid-open No. 192476/95 and Japanese Patent Laid-open No. 93978/95. In this method, dummy cells are prepared in which logic "1" and "0" are respectively written to two ferroelectric capacitors, data are read from both dummy cells, and the reference potential is generated by averaging their values.
The method disclosed in Japanese Patent Laid-open No. 93978/95 will be described with reference to FIG. 1. In the figure, logic "1" and "0" are written in dummy cells DMCa1 and DMCa2, respectively. After precharging bit lines BLa1 and BLa2, dummy cells DMCa1 and DMCa2 are selected by word lines DWLa1 and DWLa2, and signal potentials corresponding to "1" and "0" are generated on bit lines BLa1 and BLa2. Thereafter, transistor TSW1 is rendered conductive by a bit line short-circuit signal to generate a voltage on the bit line corresponding to the midpoint between "1" and "0". If a read from memory cell MCa1 takes place after rendering transistor TSW1 non-conductive and again precharging bit line BLa1, then bit line BLa1 becomes a potential corresponding to "1" or "0" read from memory cell MCa1 and bit line BLa2 becomes a potential corresponding to the midpoint between "1" and "0", thereby providing a one-transistor one-capacitor type ferroelectric memory device. Japanese Patent Laid-open No. 192476/95 discloses a construction in which the reference potential generated in a dummy cell is stored in an electronic memory unit to avoid subsequent generation of the reference potential. Thus, deterioration of the dummy cell due to film fatigue can be suppressed.
Other examples of dummy cell construction are disclosed in, for example, Japanese Patent Laid-open No. 301093/90 and U.S. Pat. No. 4,873,664 in which the size of the ferroelectric capacitor of dummy cells is made different from that of memory cells, in order to generate a reference potential.
The method disclosed in Japanese Patent Laid-open No. 301093/90 will be next described with reference to FIG. 2. In the figure, a signal potential is generated on bit line BLal by selecting memory cell MCa1 by means of word line WLa1 and by driving plate line PLa1. Dummy cell DMCa1 is selected by word line DWLa1, and a reference potential is generated on bit line BLa2 by driving plate line DPLa 1. The capacitor size in the dummy cell is made smaller than that of the memory cell, and moreover, the polarization direction is set such that polarization inversion always occurs when a reference potential is generated. In addition, CFa1 is selected such that its capacitance when polarization is not inverted is smaller than the capacitance of DCFa1 during polarization inversion. The capacitance of DCFa1 is therefore smaller than the capacitance of CFa1 during polarization inversion and greater than the capacitance when polarization is not inverted. A signal potential can thus be generated at BLa2 that corresponds to the midpoint between logic "1" and "0". Although the size of DCFa1 is made smaller than that of CFa1 in the above-described method, as disclosed in U.S. Pat. No. 4,873,664, the same effect can be obtained by both making DCFa1 bigger than that of CFa1 and by setting the direction of polarization such that polarization inversion never occurs when the reference potential is generated.
Another example of a dummy cell construction is described in Japanese Patent Laid-open No. 114741/93. In this example, a capacitor using a normal dielectric is employed as the capacitor of the dummy cell, and the accumulated charge of the dummy cell capacitor is used to boost the read-out signal potential such that the precharge potential is a potential corresponding to the midpoint between logic "1" and "0".
This method will be described is detail with reference to FIG. 3. In the figure, VCC/2 is supplied from the outside to one terminal of memory capacitor CFa1. Memory cell MCa1 is selected by word line WLa1, and the signal potential is generated on bit line BLa1. Dummy cell capacitor DCa1 is selected by dummy cell word line DWLa1, and boosts the potential of bit line BLa1. During a read operation, bit lines BLa1 and Bla2 are first precharged to VCC, following which word line WLa1 is selected and data are read into the bit lines. Dummy cell word line DWLa1 is then selected and the bit line potential is boosted. The capacitance used for the dummy cell at this time is such that the bit line potential when boosted is higher than the precharged potential when data is logic "1" and lower than the precharged potential when data is logic "0". As a result, the precharge potential of BLa2 is used as the reference potential, data can be sensed by sense amplifier SA.
In another method of generating a reference voltage, a reference voltage is generated in a memory cell without using a dummy cell. As an example, U.S. Pat. No. 5,086,412 discloses one such reference voltage self-generating system. According to this form, reads are carried out twice consecutively from the same memory cell, the charge read the second time being taken as the reference voltage. Explanation is presented using FIG. 4, FIG. 5, and FIG. 6 and citing the above-described U.S. Pat. No. 5,086,412. Memory cell MCa1 is selected by word line WLa1 after precharging bit line BLa1, and when plate line PLa1 is strobed (returning to the initial state after the plate line is strobed), a charge .DELTA.Q1 is read on bit line BLa1 by the transition from state A by way of state B to reach state C of FIG. 5 when the data is logic "1". When the data is logic "0", .DELTA.Q0=0 is read on bit line BLa1 because the transition is from state C to state B and then back to state C. The read charge is held in a sample & hold circuit by making TG1 "H". A second read is then carried out with respect to the same cell. Because memory cell MCa1 has been subjected to a destructive read, the second read charge is sure to be .DELTA.Q0, and the charge at the second read is therefore the reference. The charge read with TG2 at "H" is held in the sample & hold circuit and data are subsequently sensed by differential sense amplifier with TG3 as "H". In addition, bias capacitor CBIAS is added to the reference-side bit line BLR of the differential sense amplifier to enable a correct reading operation even in a case in which .DELTA.Q0=0 for both the first and second read charges. The addition of this bias capacitor CBIAS has the effect of adding an offset between the two inputs of the differential sense amplifier by changing the impedance of the bit line, thereby enabling a 1-transistor 1-capacitor type ferroelectric memory device that does not require a dummy cell.
The hysteresis characteristic of the ferroelectric shown in FIG. 22 deteriorates with increase in retention time or with ferroelectric film fatigue depending on the number of times the memory cell is accessed. In other words, the hysteresis loop of the ferroelectric film of a memory cell in which the hysteresis loop is repeatedly reversed decreases due to fatigue. FIG. 23 shows the effect upon the read bit line voltage brought about by increase in the number of access times due to this fatigue effect. In other words, in "1" reads, which accompany polarization inversion, the read voltage decreases with increase in the number of read operations, but the read voltage is fixed and unaffected by the number of read operations for "0" reads, in which polarization inversion does not occur. In addition, the "1" and "0" read bit line voltage changes according to the number of times of access as shown in FIG. 24 and FIG. 25 in cases in which the deterioration of hysteresis is imprinted, i.e., when voltage of only one direction is applied to the ferroelectric. In other words, when the bit line capacitance CB is large, "1" and "0" read voltage decreases with increase in the number of read operations. When the bit line capacitance CB is small, the "1" read voltage increases with the number of times of access, and the "0" read voltage decreases with the number of times of access.
Furthermore, the read bit line voltage also changes with increase in the retention time of data as shown in FIG. 26, the read voltage decreasing with retention time for "1" reads that accompany polarization inversion, and the read voltage being fixed with no dependency on retention time during "0" reads.
With regard to the first of the methods in which the reference voltage is generated using dummy cells, i.e., a method in which data are read from two dummy cells in which "1" and "0" are respectively written, the values averaged, and the reference voltage generated as shown in FIG. 1, there is a problem that an accurate reference voltage cannot be generated due to the difference in frequency of access between memory cells and dummy cells over a great number of times of use. The same problem exists for Japanese Patent Laid-open No. 192476/95. The same problem also exists with regard to the second dummy cell method, i.e., the method shown in FIG. 2 in which the size of the dummy cell capacitor is made to differ from that of the memory cell capacitor and this difference then used to generate a reference voltage. Moreover, this problem cannot be avoided even in the third dummy cell method, i.e., the method shown in FIG. 3 in which a normal dielectric film is used in the dummy cell capacitor.
In addition, the difficulty of designing the dummy cell capacitor size can be raised as another problem in the second dummy cell method (FIG. 2). This problem arises because the dummy cell capacitor size is determined by estimating the capacitance during inversion and non-inversion of polarization of the dummy cell capacitor based on an advance estimate of the capacitance of the memory cell capacitor. This problem also exists for the third dummy cell method, i.e., the case in which a normal dielectric film is used in the dummy cell capacitor as shown in FIG. 3.
As yet another problem in the method of FIG. 4 in which reference voltage is generated within cells themselves without employing dummy cells, a precise reference voltage cannot be generated and the read margin of logic "1" becomes narrow. In concrete terms, the actual read charge for logic "1" is lower than .DELTA.Q1 in FIG. 5, and the charge that contributes to the reference voltage is greater than .DELTA.Q0, resulting in the problem that the read margin of logic "1" becomes narrow in the unaltered prior-art example. This problem occurs because the effect of bit line capacitance is not considered among the principles of read-out in the prior-art example shown in FIG. 5. The read operation of the prior art is next investigated again with proper consideration given to the bit line capacitance using FIG. 7. In the figure, the straight line represents the load line arising from the bit line capacitance. When logic "1" is read, .DELTA.Q1 makes a transition on hysteresis from state A through B and actually reaching C, .DELTA.Q1 becoming the charge that is read and thus becoming a value lower than .DELTA.Q1 shown in FIG. 5. After reading of logic "1", moreover, the state makes a transition to C rather than to E as explained in the prior-art example, and the reference therefore becomes .DELTA.Qref1, which is greater than .DELTA.Q0 in a subsequent reference read. As a result, in some cases .DELTA.Q1.apprxeq..DELTA.Qref1, i.e., the charge at "1" reads and reference reads become nearly equal and the read margin narrows. In addition, a bias capacitor is provided in the prior-art method to correctly read logic "0", thus establishing an offset between .DELTA.Q0 and .DELTA.Qref0. In states in which .DELTA.Q1.apprxeq..DELTA.Qref1, however, this offset causes erroneous operation in which a "1" read is read as "0", and a correct read operation therefore cannot be expected in the prior-art method.
Yet another problem in the method shown in FIG. 4, in which the reference voltage is generated without using dummy cells, is slow access speed. This problem is caused by the large number of transitions of the plate line. In concrete terms, the plate line must make a transition from "L" to "H" and from "H" to "L" four times for a read of data from a memory cell and twice for rewriting in the prior-art example. The time constant is great because plate line wiring is generally long and a plurality of memory cells are connected. High-speed access therefore cannot be expected in the methods of the prior art.